Posted May 27, 2013

ASIC/SoC/FPGA Lead/Senior Design Engineer (Refrence DSTL001)

Silicon Vision is seeking Sr/Lead ASIC/SoC/FPGA Design Engineers to work at its headquarter office in Cairo. The successful candidate will provide hands-on technical design leadership and be an individual contributor on ASIC/SoC and FPGA projects. The candidate will be responsible for, and contributing to, all phases of an ASIC/SoC/FPGA development starting from creation of an architectural specification through ASIC/SoC/FPGA sign-off. 

Summary:
The ASIC/SoC/FPGA Lead/Senior Design Engineer position is part of a team responsible for all aspects of development of block and full chip RTL netlists, including design, audits, physical implementation and block level verification. In this role, there will be significant interaction with other design engineers.

Responsibilities:
Design and verify digital RTL blocks that are implemented in standard cell ASIC and/or FPGA.
Implement technical specification and/or design implementation documents. The RTL designs may be created in-house, obtained from a 3rd party IP vendor or from a customer.
Implement design with VHDL and/or Verilog.
Verify block design with Verilog or SystemVerilog testbenches. Knowledge of UVM or OVM a plus.
Perform design audits, synthesis, static timing analysis, equivalence checking, SCAN insertion, ATPG.
Support layout engineers by providing design constraints and assisting with floor-planning.
Work with architect, marketing, and applications engineering to ensure finished product meets technical specifications and customers' needs.
Work with project manager to ensure product is delivered on schedule.
Support application and software teams with functional models and SW/HW co-verification issues.
Support test and validation teams with ATE and board-level test issues.
Support technical development of junior engineers.

Qualifications: 
BS or MS in Electrical Engineering or Computer Engineering.
8+ years of ASIC design and verification experience.
Experienced in ASIC design flow (RTL design, simulation, synthesis, clock tree insertion, static timing analysis and timing closure, equivalence checking, DFT, ATPG). Key tools include Modelsim, Cadence RC, Synopsys Design Compiler, Formality, Primetime, Galaxy Constraint Audits, and Subversion/Synchronicity. Knowledge of Place and Route tools such as Synopsys ICC is a plus.
Proficient in Verilog HDL and SystemVerilog. UVM or OVM knowledge preferred.
Experience in deep-submicron ASIC design at 90 nm or less preferred. Experience with high speed RTL block design in excess of 300 MHz is also preferred. Experience in techniques for low power implementation is also preferred.
Proficient in Perl, Tcl and Unix/Linux shell scripting. Object-oriented programming skill is a plus.
Knowledge of standards (Ethernet, PCIe, JTAG, SPI, I2C, DDRx memory interfaces) preferred.
Experince in projects planning and projects managing is required.
Good teamwork and able to collaborate with multi-site teams.
Good written and verbal communication skills.

Company Offers:
A stimulating, exciting and dynamic work environment, where your personal contributions to our business success will be optimally rewarded
Room for career growth and external training.
A competitive packages including excellent salaries, health insurance for employees and their families, bonus system and stock options

How to apply:
Please send your updated resume to [email protected] and add DSTL001 in email subject. only emails following this format will be considered.