Posted Jun 05, 2013
Senior IC Layout/CAD Engineer - [REF SICLE]
• Leading the integration of IC chip using Cadence and Mentor tools in a timely fashion.
• Performing post-layout verification (DRC, LVS, etc) and parasitic extractions and debugging such issues.
• Interacting with design team to establish layout requirements and constraints following the integration process
• Creating analog modules to automate (as possible) analog layout & Chip integration
Experience / Requirements:
• A B.Sc./M.Sc in Electrical Engineering, with an ability to lead layout team in performing layouts & chip integration following the process in timely fashion.
• Experience (+4) in floor-planning, placement, layout, layout verification, chip integration and parasitic extraction.
• Experience (+4) in working with different EDA tools such as Cadence, Cadence Virtuoso, Calibre, and Mentor Graphics.
• Shell or SKILL scripts writing experience is a plus.
• Must be self-motivated
To apply send your CV to firstname.lastname@example.org and indicate the position in the subject of the email.