Digital Design Engineer (REF: DSE001) (multiple levels seniors/juniors)
Silicon Vision announcing for the need of Digital Design Engineer (REF: DSE001) (multiple levels seniors/juniors):
Our group offers a unique opportunity to grow your digital design skills while you assist with the development of different types of ASICs. Your duties will include Verilog/VHDL coding, functional verification, synthesis, and timing analysis.
-Develop and execute detailed block-level and chip-level digital designs. -Write and verify RTL code (Verilog/VHDL) for digital sub-systems of system-on-a-chip (SOC). -Synthesis of RTL code. -Run static timing verification on the gate-level netlist with parasitics -Writing test plans and test-bench development. -Generation of required documentation and contribution to the validation and debugging of the fabricated silicon.
-BS or MS in Electrical Engineering with background in CMOS ASIC/FPGA design -At least 3 years of industry experience is desired (for senior positions) -Design and verification experience at the RTL and gate-level (Verilog/VHDL) -Experience with synthesis tools -Working knowledge of Cadence's and Mentor IC design and verification tools on (NC--SIM, AMS-designer, ModelSim, etc). -Knowledge of high speed and low power digital design techniques -Strong documentation, communication, and presentation skills. -Excellent problem solving and analytical skills. -Must exhibit technical leadership and have experience with team building, process improvement, conflict resolution, and motivating people. -Knowledge of P&R and DFT tools is a plus.
-A stimulating, exciting and dynamic work environment, where your personal contributions to our business success will be optimally rewarded -Room for career growth and external training. -A competitive packages including excellent salaries, health insurance for employees and their families, and bonus system
If you are interested, please send your updated resume along with your contact details to email@example.com. Please type only DSE001 in email's subject.