Posted Jun 11, 2013
Senior IC Layout Designer Open Vacancy (REF: LE010)
- Candidate will be responsible for both cell-level and top-level IC layout using Cadence and Mentor Graphics tool sets (Virtuoso Layout Editor, Assura, Calibre).
- Working on the development of predominantly RF/mixed-signal IC's with increasing levels of digital core integration against time.
-Will be responsible for automatic place and route layout techniques for some digital blocks using Encounter.
- Will be responsible for the whole project from the layout point of view till the tape-out date.
- Will work as part of a layout IC team on large projects.
- Will lead some layout designers during projects.
- Will work closely with the IC design team throughout the design cycle to understand design requirements/layout constraints, and to support parasitic extraction, post layout verification and analysis.
-Will work closely with semiconductor foundries to submit the final GDSII and database and fill the required forms for the tape out
- +3 Years of experience in IC layout and (or) CAD using Cadence and (or)
Mentor layout tools.
- Strong knowledge RF and multi-GHz SerDes Layout techniques.
- Experience with 65-nm technology and lower is beneficial.
- Experience with logic core standard-cell place and route is beneficial.
- Good knowledge of analog and RFIC layout techniques is a must.
- Shell scripting, Perl, and skill scripting knowledge are a plus.
- A hands on experience in state of the art technologies and deep sub-micron
processes is preferred.
- Good understanding of process design kit set-up and configuration for Mentor
or Cadence based kits would be advantageous.
- B.Sc./M.Sc. in Electronics Engineering.
- Excellent communications skills, written and spoken.
- Ability to work independently as well as a key team player.
- Oral and written fluency in English.
Interested candidates should send their resumes to firstname.lastname@example.org.
Please include "LE010_Name_GraduationYear" in the e-mail subject.