Designing analog circuits on deep sub-micron process technologies (32, 22, 14, 10, 7, 5 nm) has its own set of challenges. With supply voltage scaling down, threshold voltages holding its values to maintain moderate leakage currents as demanded by low power designs for modern and mobile gadgets, the headroom is running out. Coupled with degraded rout and denser metal stack, stringent design and density rules make analog design even tougher, especially for high yield products that are required to ship hundreds of millions of units with very low wafer cost. This focused class is intended to address these challenges from an industrial view point, starting from the basics, building its way up to designing advanced analog blocks in deep submicron process nodes, while keeping yield as the number one challenge.
Course Description: *************** 1) Setting the stage: a. Introduction, basic transistor operation b. What to expect out of the fellow transistor in 22nm and beyond. c. Device matching considerations….in 22nm??
2) Building Block design in deep sub-micron a. Bias, can it still be global? b. Different topologies of bias circuitry c. Band gap……good luck!!! d. Bias stability and matching considerations…why do you keep repeating matching?! e. Diff amp, …still? f. Opamps….you must be kidding, again !!!, all types?? g. VCO…..yes!! this is to be called a cool guy!! h. DC-DC converters…yucky!!
3) Noise…this is the part that I don’t like…not cool!! 4) Analog layout…come on, I will just copy it from a friend.
5) Yield considerations a. PVT b. Bias c. How many sigmas?