2013 VLSI ACADEMY ASIC DESIGN WORKSHOP

Instructor: 
Eng. Amr Lotfy
Date: 
Jun 23 - Jul 6  2013

Time:   9:30 am -1:30 pm


Location

Lab 5, Third Floor, Electrical Department Building
Faculty of Engineering - Alexandria University


Instructor

Amr Lotfy received the B.Sc. degree in electrical engineering from Alexandria University, in 2008 and the M.S degree in Microelectronic Systems Design from Nile University in 2011. From 2009 to 2010, he was with Intel Architecture Group (IAG), Hillsboro OR, USA, working on the design of high performance digital phase locked loops. Currently he is a research scientist and consultant in the wireless sensors group at Intel Egypt. His research is focusing on high performance clock generation circuits for microprocessors and high speed links. Amr is a technical reviewer for the IEEE TCAS-I and TVLSI Journals.


Workshop Description

Modern digital VLSI chips, like microprocessors, contain billions of transistors and thousands of logic gates. The design of such chips is quite complex and require many phases of testing and verification. This workshop provides a hands-on illustration of taking an ASIC from RTL to tape-out


Agenda

• June 23  - Session 1: RTL Design Using Verilog.
  
• June 24   - Session 2: Synthesis (RTL to gate level netlist).
  
• July 4   -  Session 3: Place & Route (Gate level netlist to GDS).
  
• July 6  - Session 4: Notes on Different Topics, Mixed Signal Simulation, Mixed Signal Validation, Chip Testing and Measurements.
  

Requirements

• Good knowledge of Verilog or VHDL.
  
• Good understanding of basics of logic design and arithmetic circuits.
  
• Understanding of digital design flow (RTL, Synthesis, Place&Route).
  
• Laptop with 100 GB of free HD space

 

Tools

• Digital Design Simulation Tool: ModelSim (Mentor Graphics).
  
• Synthesis Tool: Design Compiler (Synopsys).
  
• Place & Route Tool: Physical Compiler (Synopsys).