Universal Verification Methodlogy (UVM) Workshop Application FORM

VLSI Egypt is proud to announce that it is organizing a "Functional Verification Workshop" with emphasis on UVM in collaboration with Boost Valley. The workshop will be given by experienced industry Engineers. The workshop will be given through three sessions in April. The class size is very limited to ensure more interactivity. Those accepted in the workshop will be eligible to a summer internship in Boost Valley in Summer 2015. All details are shown below. Please apply using the form below and note that the application deadline is Friday 27/03/15 @11:59pm. Accepted applicants will be informed via email. 

Sessions Dates :

• Session 1: Wednesday 1/4/15 @  7 PM
  
• Session 2: Monday       5/4/15 @ 10 AM
  
• Session 3: Sunday      12/4/15 @ 7 PM
  

Address:

• Boost Valley premises, 4 Hassan Allam St, Heliopolis, Cairo, Egypt
  

Sessions Pre-requisites:

• Object oriented concepts knowledge is a must
  
• Verilog knowledge is a must
  
• System Verilog is a plus
  

Course content

• TLM introduction
  
• UVM Testbench Structure
  
• TLM in UVM
  
• UVM Management
  
• UVM Factory
  
• TestBench blocks in details
  
• Transactions
  
• UVM Sequences
  
• Analysis
  
• Real Life example